hv5630 general description the hv5630 is a low-voltage serial to high-voltage parallel converter with open drain outputs. this device has been designed for use as a driver for ac-electroluminescent displays. it can also be used in any application requiring multiple output high voltage current sinking capabilities such as driving inkjet and electrostatic print heads, plasma panels, vacuum ?uorescent, or large matrix lcd displays. this device consists of a 32-bit shift register, 32 latches, and control logic to perform the polarity select and blanking of the outputs. data is shifted through the shift register on the high to low transition of the clock. the hv5630 shifts in the clockwise direction when viewed from the top of the package. a data output buffer is provided for cascading devices. this output re?ects the current status of the last bit of the shift register. operation of the shift register is not affected by the le (latch enable), bl (blanking), or the pol (polarity) inputs. transfer of data from the shift register to the latch occurs when the le (latch enable) input is high. the data in the latch is stored when le is low. functional block diagram 32-channel serial to parallel converter with open drain outputs polarity blanking latch enable data input clock data out 32-bit shift register hv ou t 1 (outputs 3 to 30 not shown) latch latch hv ou t 2 hv ou t 31 hv ou t 32 latch latch features processed with hvcmos ? technology sink current minimum 100ma shift register speed 8.0mhz polarity and blanking inputs cmos compatible inputs forward and reverse shifting options diode to vpp allows ef?cient power recovery ? ? ? ? ? ? ?
2 hv5630 ordering information device package option 44-lead quad plastic chip carrier .690x.690in body .180in height (max) .050in pitch hv5630 hv5630pj-g -g indicates package is rohs compliant (green) absolute maximum ratings supply voltage, v dd 1 -0.5v to +15v output voltage, v pp 1 -0.5v to +315v logic input levels 1 -0.5v to v dd +0.5v ground current 2 1.5a continuous total power dissipation 3 1200mw operating temperature range -40 o c to +85 o c storage temperature range -65 o c to +150 o c lead temperature 4 260 o c parameter value sym parameter min max units recommended operating conditions v dd logic voltage supply 10.8 13.2 v hv out high voltage output -0.3 +300 v v ih input high voltage v dd -2.0 v dd v v il input low voltage 0 2.0 v f clk clock frequency - 8.0 mhz t a operating free-air temperature -40 +85 o c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. notes: all voltages are referenced to v ss duty cycle is limited by the total power dissipated in the package for operation above 25c ambient derate linearly to maximum operating temperature at 20mw/c 1.6mm (1/16inch) from case for 10 seconds 1. 2. 3. 4. power-up sequence power-up sequence should be the following: connect ground apply v dd set all inputs to a known state power-down sequence should be the reverse of the above. 1. 2. 3. pin con?gurations 1 44 6 40 yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = green packagin g *may be part of top marking top marking bottom marking yyww hv5630pj llllllllll ccccccccccc aaa 44-lead plcc (pj) (top view) product marking 44-lead plcc (pj)
3 hv5630 sym parameter min max units conditions electrical characteristics (over recommended operating conditions unless otherwise noted) dc characteristics ac characteristics (v dd = 12v, t c = 25 o c) sym parameter min max units conditions f clk clock frequency - 8.0 mhz --- t w clock width, high or low 62 - ns --- t su data set-up time before clk falls 25 - ns --- t h data hold time after clk falls 10 - ns --- t on turn-on time, hv out from enable - 500 ns r l = 2.0k to v pp max. t dhl delay time clock to data high to low - 100 ns c l = 15pf t dlh delay time clock to data low to high - 100 ns c l = 15pf t dle delay time clock to le low to high 50 - ns --- t wle width of le pulse 50 - ns --- t sle le setup time before clock falls 50 - ns --- i dd v dd supply current - 15 ma f clk = 8.0mhz, f data = 4.0mhz i ddq v dd supply current (quiescent) - 100 a v in = 0v i o(off) off state output current - 10 a all outputs high, all sws parallel i ih high-level logic input current - 1.0 a v ih = v dd i il low-level logic input current - -1.0 a v il = 0v v oh high-level output data out v dd -1.0v - v i dout = -100a v ol low-level output voltage hv out - 15 v i hvout = +100ma data out - 1.0 v i dout = +100a v oc hv out clamp voltage - -1.5 v i ol = -100ma input and output equivalent circuits vdd inpu t hvou t logic inputs data ou t logic data outpu t high voltage outputs vdd hvi n vss vss vss
4 hv5630 switching waveforms latch enable hv out w/ s/r high data valid 50% 50 % data input clock data ou t 50% 50% 50% t su t h t wh t wl 50 % 50 % t dlh t dh l 50 % t wle t dle t sle 50 % 50 % 10 % t on v i h v i l v ih v il v o h v o l v oh v o l v ih v i l v o h v ol functional table function inputs outputs data clk le bl pol shift reg hv outputs data out * 1 2...32 1 2...32 all on x x x l l * *...* on on...on * all off x x x l h * *...* off off...off * invert mode x x l h l * *...* * *...* * load s/r h or l l h h h or l *...* * *...* * load latches x h or l h h * *...* * *...* * x h or l h l * *...* * *...* * transparent latch mode l h h h l *...* off *...* * h h h h h *...* on *...* * notes: h = high level, l = low level, x = irrelevant, = high-to-low transition, = low-to-high transistion. * dependent on previous stages state before the last clk or last le high.
5 hv5630 44-lead plcc pin assignment (pj) pin function description 1 hv out 17 high voltage outputs. 2 hv out 16 3 hv out 15 4 hv out 14 5 hv out 13 6 hv out 12 7 hv out 11 8 hv out 10 9 hv out 9 10 hv out 8 11 hv out 7 12 hv out 6 13 hv out 5 14 hv out 4 15 hv out 3 16 hv out 2 17 hv out 1 18 data out data output pin. 19 n/c no internal connection. 20 n/c 21 n/c 22 pol inverts the polarity of the hv out pins 23 clk clock pin, shift registers shift data on falling edge of input clock. 24 vss reference voltage, usually ground. 25 vdd logic supply voltage. 26 le latch enable pin, data is shifted from shift register to latches on logic input high. 27 data in data input pin. 28 blanking blanking pin sets all hv out pins low or high depending upon state of polarity. see function table. 29 n/c no internal connection. 30 hv out 32 high voltage outputs. 31 hv out 31 32 hv out 30 33 hv out 29 34 hv out 28 35 hv out 27 36 hv out 26 37 hv out 25 38 hv out 24 39 hv out 23 40 hv out 22 41 hv out 21 42 hv out 20 43 hv out 19 44 hv out 18
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. website: http//www .supertex.com . ?2008 all rights reserved. unauthorized use or reproduction is prohibited . 1235 bordeaux drive, sunnyvale, ca 9408 9 te l: 408-222-8888 www .supertex.com 6 hv5630 doc.# dsfp-hv5630 a092508 44-lead plcc package outline (pj) .653x.653in body, .180in height (max), .050in pitch symbol a a1 a2 b b1 d d1 e e1 e dimension (inches) min .165 .090 .062 .013 .026 .685 .650 .685 .650 .050 bsc nom .172 .105 - - - .690 .653 .690 .653 max .180 .120 .083 .021 .036 ? .695 .656 .695 .656 jedec registration ms-018, variation ac, issue a, june, 1993. ? this dimension is a non-jedec dimension. drawings not to scale. supertex doc. #: dspd-44plccpj, version d092408. .150 ma x .048/.042 x 45 o 1 .075 ma x 6 40 d d1 e1 e to p v iew horizontal side v iew v iew b a a2 a1 seating plane e b note 1 (index area) .056/.042 x 45 o .020max (3 places) .020 min ve rtical side v iew v iew b note 2 44 b1 base plane notes: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. actual shape of this feature may vary. 1. 2.
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